Multichip module

ABSTRACT

A bondwire transition arrangement for interconnecting a signal port on one IC of a multichip module with a signal port on another, adjacent, IC of the same module employs a distributed signal-transition process in which the signal on one port appears as subsignals at tapping points along a series transmission-line segment arrangement between that port and ground on the same IC and the subsignals are recombined along a second series transmission-line segment arrangement connected between the other port and ground on the other IC. Spatially corresponding tapping points are interconnected via bondwires.

The invention relates to a multichip module having two or more microwavecircuits which are interconnected by way of bondwires, and in particulara multichip module in which the microwave circuits are MonolithicMicrowave Integrated Circuits (MMICs) or Microstripline IntegratedCircuits (MICs).

Due to the ongoing demand for compact and small systems, more and moreintegrated circuits (ICs) are being used in microwave systems andsubsystems. These ICs take the form of either MICs or MMICs. AlthoughMMICs are the dominant components in the design of present and futuremicrowave systems, in practice microwave systems comprise a mixture ofthese two components plus a number of lumped elements, e.g. inductors,resistors and capacitors, which cannot be integrated in the same way.These are all assembled together onto a Multichip Module (MCM), thevarious components being interconnected by means of bond- or leadwires.

The bondwires are kept as short as practicable as compared to theoperating wavelength of the various circuits being interconnected, sothat they do not affect the electrical characteristics of the MMICs orMICs at low frequency. Notwithstanding this, significant effects onelectrical characteristics have been observed at high frequency, thesecharacteristics including the scattering parameters and noise of theICs. Thus the bondwire interconnection plays a major role in the designand integration of the multichip module, a role which the IC designerhas to take into account.

The bondwire is most commonly considered as a lumped inductance, butthis simple model is complicated at high frequencies due to thefollowing factors:

-   (a) Parasitic capacitances are associated with the bondwire, not    simply inductance.-   (b) Where more than one bond wire is used in parallel there is a    proximity effect, which complicates the picture.-   (c) The presence of two or more dielectrics makes it even more    difficult to calculate the dispersive properties of the    interconnections.-   (d) Bondwire resistance has to be taken into account and skin effect    at high frequencies is especially significant; the high-frequency    resistance may be many times its DC value.

The bondwire transition between the ICs is mainly made up of inductancetogether with some parasitic capacitance, and as such possesses aninherently low-pass characteristic. In order to be usable at highfrequency a bondwire interconnection needs to be compensated. Thefollowing known methods are used to achieve this:

(1) The bond wires are kept as short as possible. FIG. 1 shows two ICchips 10 and 11, each having a signal port 12, 13 to which are connectedrespective transmission-line segments 14, 15 which terminate inrespective bondpads 16, 17 very near the edge of the chips. Joining thetwo bondpads is a short bondwire 18. There are physical limitations tothis scheme, however; for example, it is difficult to realise incascaded assemblies due to manufacturing tolerances.

(2) Two or more bondwires are connected in parallel to reduce theinductance (see FIG. 2), but that requires a bigger bondpad, which inturn means a larger parasitic capacitance, and this again limits thebandwidth.

(3) One or two lumped capacitances 19, 20 are attached in series withthe bondwire as shown in FIG. 3. This gives rise to a bandpasscharacteristic, with the result that such transitions can be used onlyin a limited bandwidth. A further drawback is that the MIM-typecapacitors, which are commonly used in MMIC technology, cannot be bondedat their top plate due to the thinness of the dielectric used in suchcapacitors. This transition arrangement can, however, be employed inMIC-to-MIC interconnections if lumped capacitors such as Di-caps® areused.

(4) Where more than one bondwire is employed, a large bondpad called a“T-shaped flare” may be used on each chip (see FIG. 2, where the twoflares are shown as items 21 and 22). The capacitors shown are theopen-end capacitances of the open-circuit stubs part of the flare. Thesecapacitances are, in fact, parasitic bond-pad capacitances. Though thisconfiguration is very common, it is limited in bandwidth due to itslow-pass characteristics.

In accordance with a first aspect of the invention there is provided amulti-chip module comprising adjacently disposed first and secondmicrowave circuits having respective first and second signal ports andrespective first and second reference-potential points, there beingconnected between the first signal port and the firstreference-potential point a first series arrangement of Ntransmission-line segments having N−1 sequential tapping points, andbetween the second signal port and the second reference-potential pointa second series arrangement of transmission-line segments having N−1sequential tapping points, wherein the signal-port end of the firstseries arrangement corresponds spatially to the reference-potential endof the second series arrangement and the signal-port end of the secondseries arrangement corresponds spatially to the reference-potential endof the first series arrangement, and likewise spatially correspondingpairs of tapping points are connected together by way of respective bondwires.

Preferably for at least one of the first and second series arrangements,the transmission-line segment nearest to the signal port is a bend.

Advantageously the first and second series arrangements areopen-circuited. Preferably in such an arrangement for at least one ofthe first and second series arrangements, an open-circuit capacitance isprovided at the reference-potential end of the arrangement.

Preferably the microwave circuits are monolithic microwave integratedcircuits (MMICs) or microstripline integrated circuits (MICs).

According to a second aspect of the invention there is provided a methodfor interfacing a signal on a first signal port of one IC of a multichipmodule with a second signal port of another, adjacent, IC of the samemultichip module, comprising: decomposing the signal into a plurality ofsubsignals in a first transmission-line arrangement; feeding thesubsignals via bondwires to a second transmission-line arrangement; andrecombining in the second transmission-line arrangement the thus fedsubsignals into a combined signal at the second signal port.

An embodiment of the invention will now be described, by way of exampleonly, with reference to the drawings, of which:

FIGS. 1, 2 and 3 are examples of known bondwire interconnections betweenintegrated circuits;

FIG. 4 is a circuit diagram of a bondwire transition in accordance withthe present invention, and

FIG. 5 is a diagram illustrating various performance characteristicsassociated with the bondwire transition of FIG. 4.

Referring now to FIG. 4, an embodiment of the invention will now bedescribed.

As already described in the previous examples, two IC chips 10 and 11(MMIC or MIC circuits) have respective signal ports 12, 13 which are tobe interconnected using bondwires. In this case, however, a distributedform of transition is achieved by the provision of respective seriesarrangements 30, 31 of transmission-line segments 32 connected betweenthe signal ports 12, 13 and reference-potential (ground) points 33, 34.The underside of each MMIC or MIC circuit is at ground potential. Theactual transition is accomplished by connecting the various tappingpoints along one series arrangement 30 to the spatially correspondingtapping points along the other series arrangement 31 by means ofbondwires 35. By arranging for the various tapping-point pairs to bedirectly opposite each other, it can be ensured that the bondwires areas short as possible, which has already been shown to be desirable. Itis important to note in this configuration that the signal-port end ofseries arrangement 30 lies more or less opposite the non-signal-port endof series arrangement 31, and vice-versa.

In this configuration, then, where the signal ports 12 and 13 are, forexample, an output port and an input port, respectively, the outputsignal to the series arrangement 30 is distributed to all the bond-wireconnections 35 and the thus created subsignals are again combined, viaseries arrangement 31, into one signal at the input port 13 of IC 11.

This type of interconnection is very broadband due to the distributednature of the transition. An idea of the typical performance of theinterconnection is given in FIG. 5, in which the magnitude (in dB) ofvarious S-parameters associated with the transition scheme are plottedagainst frequency.

In the actual embodiment shown in FIG. 4 a total of fivetransmission-line segments are shown in each series arrangement 30, 31,with the segment nearest the signal port in each case being a mitredbend 36. The last transmission-line section 32 nearest the ground end 33is in each case an open-circuit stub and the capacitances 37 and 38 arethe open-end capacitances of these stubs. Depending on the layout of theparticular IC chips involved, a mitred bend might not be needed, alsothe number of segments may be more or less than the five shown. Thenumber of bond wires 35 and transmission lines 32 are the criteria whichdetermine the bandwidth and reflection coefficient of the transition.

In practice the parameter-values of the various transmission-linesegments 32 of the series arrangement 30 may be different from eachother, and likewise the parameter-values of the segments 32 of theseries arrangement 31. Also the parameter values of correspondingsegments, e.g. segments 39 and 40, may be different from each other. Thedesign is based upon a multiple branch line zero-dB coupler, wherebond-wires 35 are branch lines and lines 30 and 31 are through- andcoupled lines. The coupled and isolated ports are terminated inopen-circuit capacitances 37 and 38.

1-6. (canceled)
 7. A multi-chip module, comprising: a) adjacentlydisposed first and second microwave circuits having respective first andsecond signal ports and respective first and second reference-potentialpoints; b) a first series arrangement of N transmission-line segmentshaving N−1 sequential tapping points being connected between the firstsignal port and the first reference-potential point; c) a second seriesarrangement of transmission-line segments having N−1 sequential tappingpoints being connected between the second signal port and the secondreference-potential point; d) the first series arrangement having asignal-port end which corresponds spatially to a reference-potential endof the second series arrangement; e) the second series arrangementhaving a signal-port end which corresponds spatially to areference-potential end of the first series arrangement; and f) likewisespatially corresponding pairs of tapping points being connected togetherby way of respective bond wires.
 8. The multi-chip module as claimed inclaim 7, wherein, for at least one of the first and second seriesarrangements, a transmission-line segment nearest to at least one of thesignal ports is a bend.
 9. The multi-chip module as claimed in claim 7,wherein the first and second series arrangements are open-circuited. 10.The multi-chip module as claimed in claim 9, wherein, for at least oneof the first and second series arrangements, an open-circuit capacitanceis provided at the reference-potential end of said at least onearrangement.
 11. The multi-chip module as claimed in claim 7, whereinthe microwave circuits are monolithic microwave integrated circuits(MMICs).
 12. The multi-chip module as claimed in claim 7, wherein themicrowave circuits are microstripline integrated circuits (MICS).
 13. Amethod of interfacing a signal on a first signal port of one integratedcircuit (IC) of a multi-chip module with a second signal port ofanother, adjacent, IC of the same multi-chip module, comprising thesteps of: a) decomposing the signal into a plurality of subsignals in afirst transmission-line arrangement; b) feeding the subsignals viabondwires to a second transmission-line arrangement; and c) recombiningin the second transmission-line arrangement the thus fed subsignals intoa combined signal at the second signal port.